DLAB=DISABLED, PS=ODD_PARITY, PE=DISABLE_PARITY_GENER, BC=DISABLED, SBS=1_STOP_BIT, WLS=5_BIT_CHARACTER_LENG
Line Control Register. Contains controls for frame formatting and break generation.
| WLS | Word Length Select. 0 (5_BIT_CHARACTER_LENG): 5-bit character length. 1 (6_BIT_CHARACTER_LENG): 6-bit character length. 2 (7_BIT_CHARACTER_LENG): 7-bit character length. 3 (8_BIT_CHARACTER_LENG): 8-bit character length. |
| SBS | Stop Bit Select. 0 (1_STOP_BIT): 1 stop bit. 1 (2_STOP_BITS): 2 stop bits. (1.5 if LCR[1:0]=00). |
| PE | Parity Enable. 0 (DISABLE_PARITY_GENER): Disable parity generation and checking. 1 (ENABLE_PARITY_GENERA): Enable parity generation and checking. |
| PS | Parity Select. 0 (ODD_PARITY): Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 1 (EVEN_PARITY): Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 2 (FORCE_HIGH): Force HIGH. Forced 1 stick parity. 3 (FORCE_LOW): Force LOW. Forced 0 stick parity. |
| BC | Break Control. 0 (DISABLED): Disabled. Disable break transmission. 1 (ENABLED): Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high. |
| DLAB | Divisor Latch Access Bit (DLAB) 0 (DISABLED): Disabled. Disable access to Divisor Latches. 1 (ENABLED): Enabled. Enable access to Divisor Latches. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |